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To enable powerful and simultaneously flexible packet processing systems, developments have been made in two key areas, which are presented here: the actual packet processing (manipulation, forwarding, discarding, sorting of packets) and packet classification. To optimize packet processing, an FPGA-based architecture for functional modules has been developed, allowing for stepwise processing of packets at data rates of 4 Gbit/s and more. Fast packet classification is a necessary prerequisite for efficient packet processing. Hash-based classification algorithms and architectures are fundamentally suitable for this purpose. To optimize this class of algorithms, an evolvable hash function architecture has been developed as part of this work, which can adapt to the existing classification requirements (the composition of the key set) based on a hardware-implemented genetic algorithm. The evolvable hash function has been implemented as part of a simple evolvable packet classifier and optimized in various areas.

Actual product image Paketverarbeitende Systeme (Harald Widiger, 2009)

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